1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices, and more specifically to electrically erasable and programmable non-volatile memory devices.
2. Description of the Related Art
Electrically erasable and programmable non-volatile memory devices (EEPROMs) offer great flexibility of use and are now one of the most widely used types of memory devices. Conventional EEPROM devices have two transistors for each memory cell (i.e., a selection transistor and a floating gate storage transistor), and each memory cell stores one bit of information. High capacity (e.g., 1 Mbit) EEPROMs have been developed to be used in applications that require a large amount of memory. Typically, such EEPROMs are delivered to the customer in a known state, such as with all memory cells placed in the erased state. Later, the customer writes the required application-specific data to the memory devices on the production line.
In particular, two successive cycles are used for the first programming of an EEPROM device. An erasure cycle sets all of the memory cells of a selected word to "1" and then a programming cycle sets selected memory cells of the word to "0".For example, if the data word to be written is "10101100", then the eight memory cells of the word are first erased to the "1" state and then the second, fourth, seventh, and eighth bits are programmed to the "0" state. Thus, the first programming operation for a conventional EEPROM device has a relatively long duration that increases proportionally with the capacity of the memory.
Previously, attempts at reducing the duration of the first programming operation have focused on reducing the time required to program or erase a memory cell or on increasing the size of a page whose memory cells can be written simultaneously. For example, the time that the programming or erasure voltage is applied can be reduced in order to reduce the duration of the programming or erasing cycle. However, the voltage application period must be long enough to prevent a decrease in the information retention time of the memory cell. Additionally, the voltage level applied to the memory cell can be increased in order to reduce the duration of the programming or erasing cycle. However, the application of a higher voltage increases the risk of causing stress on the gate oxide of the memory cell. Thus, the physical characteristics of conventional EEPROM devices dictate a minimum programming cycle time and a maximum programming voltage level.
Similarly, while the duration of the first programming operation can also be reduced by increasing the page size, eventually the increased page size causes the load pump that produces the high programming voltage to be incapable of providing a sufficient voltage. More specifically, the increasing of the page size causes the capacitive load connected to the output of the load pump to be increased so it becomes necessary to increase the fan-out of the load pump. Additionally, the increasing of the page size makes it necessary to increase both the number of bit lines and the number of programming circuits in order to allow more memory cells to be programmed in parallel. Therefore, increasing the page size results in increased manufacturing cost for the device.